Yonsei University
M.S./Ph.D. in Electrical and Electronic Engineering
Seoul, South Korea
Mar. 2024 – Present
Education
Seoul National University of Science and Technology (SeoulTech)
B.E. in Electronic and IT Media Engineering
Seoul, South Korea
Mar. 2019 – Feb. 2024
Experiences
Compiler Optimization Research Laboratory (CoreLab)
Graduate Research Assistant
Yonsei University
Mar. 2024 – Present
Korea Institute of Science and Technology (KIST)
Internship Student
AI and Robotics Institute
Feb. 2023 – Sep. 2023
Publications
Refereed Journal Publications
Peak-Memory-aware Partitioning and Scheduling for Multi-tenant DNN Model
Inference
in Journal of Systems Architecture, January 2026.
IF=4.1, Q1 (JCR 2025)
Refereed Conference Publications
TeMCO: Tensor Memory Compiler Optimization across Tensor Decompositions in
Deep Learning Inference
in Proceedings of the 53rd International Conference on Parallel Processing
(ICPP), August 2024.
Refereed Poster Publications
Approximation-based Inter-PE Communication-free Image Filtering for Commodity
PIM
in Proceedings of the 62th Annual Design Automation Conference 2025 -
(Poster) (DAC), June 2025.
Patents
Method of Filtering Image
KR Patent App. 10-2025-0181300, November 2025.
Electronic Device for Performing Inference by Partitioning Neural Network Model
in Multi-tenant Environment and Operating Method thereof
KR Patent App. 10-2025-0130051, September 2025.
Device and Method with Control of Neural Network Bit Precision
KR Patent App. 10-2025-0016828, February 2025.
Compile Method and Apparatus for Neural Network
KR Patent App. 10-2024-0088419, July 2024.
Activities
International Conference Organizing Assistant
Student Volunteer
Serving as registration center at the 58th IEEE/ACM International
Symposium on Microarchitecture (MICRO)
Oct. 2025