Profile

I am a graduate student in the School of Electrical and Electronic Engineering at Yonsei University. I am a member of the Compiler Optimization Research Lab at Yonsei University, advised by Prof. Hanjun Kim. Prviously, I completed my B.S. in Creative IT Engineering at POSTECH. I am working as a visiting scholar in the High Performance Architecture Lab in Georgia Institute of Technology, advised by Prof. Hyesoon Kim.

My research interest lies in graph processing and deep learning compiler. I've worked on developing graph processing framework and deep learning compiler using MLIR. I also have experience about High-level synthesis, neural network for real-time systems, and encryption-based privacy-preserving cloud computing framework.

My Curriculum Vitae is PDF.

If you are interested in my research projects, please feel free to contact me by email.

Education

Yonsei University, Seoul, Republic of Korea, Integrated M.S./Ph.D. Student, March 2019 to Present, Advisor: Prof. Hanjun Kim

Pohang University of Science and Technology (POSTECH), Pohang, Republic of Korea Bachelor of Science in Creative IT Engineering, March 2015 to February 2019

Gwangju Science Academy for the Gifted, Gwangju, Republic of Korea High school, March 2012 to February 2015

Publications

Experience

about Computer Science

Research Assistant, March 2019 to Present

Compiler Research Laboratory (Corelab), Younsei University, Seoul, Republic of Korea

Develop thread-aware area optimized high-level synthesis framework for IoT devices (CGO 2021)

Design dynamic neural networks for real-time systems (ECRTS 2022)

Design graph processing interface to enlarge design space for GPU (PACT 2022)

Develop locality-aware graph topology layout for GPU

Visiting Scholar, March 2023 to Feb 2024

High Performance Architecture Lab(HPArch), Georgia Tech, GA, USA

Advisor : Prof. Hyesoon Kim

Develop compiler of the Open Source GPU, Vortex GPU

Expand the application support of the Vortex GPU

Undergraduate Research Assistant, December 2017 to June 2018

Compiler Research Laboratory (Corelab), POSTECH, Pohang, Republic of Korea

Develop interactive outdoor advertisement system that recommends advertisements based on eyes pose, facial expression, age, and gender data

Undergraduate Research Assistant, June to August 2016, January to February 2017

POSTECH Database and Data Mining Lab (Big data lab), POSTECH, Pohang, Republic of Korea

Design Natural Language processing system for Korean

Undergraduate Student Intern, September to December 2016

Excem, Pohang, Republic of Korea

Develop alarm system and web UI for cloud server

Exchange Student, September to December 2015

University of California, Berkeley, United States of America

International Journal Reveiwer

Reviewer, ACM Transactions on Architecture and Code Optimization, 2023

International Conference Sub-reviewer

Sub-reviewer, The 20th ACM/IEEE International Symposium on Code Generation and Optimization (CGO), 2022

Sub-reviewer, 2021 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2021

Sub-reviewer, The 19th ACM/IEEE International Symposium on Code Generation and Optimization (CGO), 2021

Sub-reviewer, Sub-reviewer, The 25th International Conference on Architectural Support for Program- ming Languages and Operating Systems (ASPLOS), 2020

Sub-reviewer, 2020 IEEE 38th International Conference on Computer Design (ICCD), 2020

Sub-reviewer, 2019 IEEE Micro

Teaching

EEE3313-01: Basic Digital Experiments, Yonsei University

Teaching Assistant, Spring 2021 (Teaching weekly lab classes about how to writing RTL Verilog code and designing hardware acceleration(FPGA- ARM))

EEE3313-01: Basic Digital Experiments, Yonsei University

Teaching Assistant, Fall 2020 (Teaching weekly lab classes about how to writing RTL Verilog code and designing hardware acceleration(FPGA- ARM))

EEE3540: Microprocessors, Yonsei University

Teaching Assistant, Fall 2019 (Teaching weekly lab classes about x86 system)

EEE3313-01: Basic Digital Experiments, Yonsei University

Teaching Assistant, Spring 2019 (Teaching weekly lab classes about how to writing RTL Verilog code and designing hardware acceleration(FPGA- ARM))

Recognition

Magna Cum Laude from POSTECH, February 2019

Excellence Award, Creative IT Design Competition, Department of Creative IT Engineering, POSTECH, June 2018

PJ Metal Best Papers, Department of Humanities and social sciences, POSTECH, December 2018

Excellence Award, 2018 POSTECH Hackathon Catch, PoApper, November 2018

Excellence Award, Arthackathon : Next-generation culture and arts education with 4th Industrial Rev- olution Technology, Jun 2018

The Grand Prize, Create IT Design Competition, Department of Creative IT Engineering, POSTECH, June 2016

Vadas Award, Create IT Design Competition, Department of Creative IT Engineering, POSTECH, December 2016

Vadas Award, Create IT Design Competition, Department of Creative IT Engineering, POSTECH, June 2016

Contact
Information

shin0403@yonsei.ac.kr
sjeong306@gatech.edu

School of Electrical and Electronic Engineering Yonsei University
Engineering Hall #3 C407
50 Yonsei-Ro Seodaemun-gu
Seoul, South Korea, 03722