Speculative Parallelization Using Software Multi-threaded Transactions [abstract] (ACM DL, PDF) Arun Raman, Hanjun Kim, Thomas R. Mason, Thomas B. Jablin, and David I. August Proceedings of the Fifteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2010.
With the right techniques, multicore architectures may be able to
continue the exponential performance trend that elevated the
performance of applications of all types for decades. While many
scientific programs can be parallelized without speculative
techniques, speculative parallelism appears to be the key to
continuing this trend for general-purpose applications.
Recently-proposed code parallelization techniques, such as those by
Bridges et al. and by Thies et al., demonstrate scalable performance
on multiple cores by using speculation to divide code into atomic
units (transactions) that span multiple threads in order to expose
data parallelism. Unfortunately, most software and hardware
Thread-Level Speculation (TLS) memory systems and transactional
memories are not sufficient because they only support
single-threaded atomic units. Multi-threaded Transactions (MTXs)
address this problem, but they require expensive hardware support as
currently proposed in the literature. This paper proposes a Software
MTX (SMTX) system that captures the applicability and performance of
hardware MTX, but on existing multicore machines. The SMTX system
yields a harmonic mean speedup of 13.36x on native hardware with
four 6-core processors (24 cores in total) running speculatively
parallelized applications.
